A conventional four transistor (4T) circuit for a pixel 150 of a CMOS imager is illustrated in FIG. 1. The 4T pixel 150 has a photosensor such as a photodiode 162, a reset transistor 184, a transfer transistor 190, a source follower transistor 186, and a row select transistor 188. It should be understood that FIG. 1 shows the circuitry for operation of a single pixel 150, and that in practical use, there will be an M×N array of pixels arranged in rows and columns with the pixels of the array being accessed using row and column select circuitry, as described in more detail below.
The photodiode 162 converts incident photons to electrons, which are selectively passed to a floating diffusion node A through transfer transistor 190 when the transistor 190 is activated by the TX1 control signal. The source follower transistor 186 has its gate connected to node A and thus amplifies the signal appearing at the floating diffusion node A. When a particular row containing pixel 150 is selected by an activated row select transistor 188, the signal amplified by the source follower transistor 186 is passed on a column line 170 to column readout circuitry (not shown). The photodiode 162 accumulates a photo-generated charge in a doped region of its substrate during a charge integration period. It should be understood that the pixel 150 may include a photogate or other photon to charge converting device, in lieu of a photodiode, as the initial accumulator for photo-generated charge.
The gate of transfer transistor 190 is coupled to a transfer control signal line 191 for receiving the TX1 control signal, thereby serving to control the coupling of the photodiode 162 to node A. A voltage source Vpix is selectively coupled through reset transistor 184 and conductive line 163 to node A. The gate of reset transistor 184 is coupled to a reset control line 183 for receiving the RST control signal to control the reset operation in which the voltage source Vpix is connected to node A.
A row select signal (Row Sel) on a row select control line 160 is used to activate the row select transistor 188. Although not shown, the row select control line 160, reset control line 183, and transfer signal control line 191 are coupled to all of the pixels of the same row of the array. Voltage source Vpix is coupled to transistors 184 and 186 by conductive line 195. The column line 170 is coupled to all of the pixels of the same column of the array and typically has a current sink 176 at its lower end. Maintaining a positive voltage on the column line 170 during an image acquisition phase keeps the potential in a known state on the column line 170. Signals from the pixel 150 are therefore selectively coupled to a column readout circuit (FIGS. 2-4) through the column line 170 and through a pixel output (“Pix_out”) line coupled between the column line 170 and the column readout circuit.
As known in the art, a value can be read from pixel 150 in a two step correlated double sampling process. First, node A is reset by activating the reset transistor 184. The reset signal (e.g., Vpix) found at node A is readout to column line 170 via the source follower transistor 186 and the activated row select transistor 188. During a charge integration period, photodiode 162 produces charge from incident light. This is also known as the image acquisition period. After the integration period, transfer transistor 190 is activated and the charge from the photodiode 162 is passed through the transfer transistor to node A, where the charge is amplified by source follower transistor 186 and passed to column line 170 through the row select transistor 188 as an integrated charge signal Vsig. As a result, two different voltage signals—the reset signal Vrst and the integrated charge signal Vsig—are readout from the pixel 150 and sent on the column line 170 to column readout circuitry, where each signal is sampled and held for further processing as known in the art. Typically, all pixels in a row are readout simultaneously onto respective column lines 170 and the column lines may be activated in sequence or in parallel for pixel reset and signal voltage readout.
FIG. 2 shows an example CMOS imager integrated circuit chip 201 that includes an array 230 of pixels and a controller 232, which provides timing and control signals to enable reading out of signals stored in the pixels in a manner commonly known to those skilled in the art. Exemplary arrays have dimensions of M×N pixels, with the size of the array 230 depending on a particular application. The pixel signals from the array 230 are readout a row at a time using a column parallel readout architecture. The controller 232 selects a particular row of pixels in the array 230 by controlling the operation of row addressing circuit 234 and row drivers 240. Signals corresponding to charges stored in the selected row of pixels and reset signals are provided on the column lines 170 to a column readout circuit 242 in the manner described above. The pixel signal read from each of the columns can be readout sequentially using a column addressing circuit 244. Pixel signals (Vrst, Vsig) corresponding to the readout reset signal and integrated charge signal are provided as respective outputs Vout1, Vout2 of the column readout circuit 242 where they are subtracted in differential amplifier 246, digitized by analog to digital converter 248, and sent to an image processor circuit 250 for image processing.
FIG. 3 shows more details of the rows and columns 249 of active pixels 150 in an array 230. Each column 249 includes multiple rows of pixels 150. Signals from the pixels 150 in a particular column 249 can be readout to sample and hold circuitry 261 associated with the column 249 (part of circuit 242) for acquiring the pixel reset and integrated charge signals. Signals stored in the sample and hold circuits 261 can be read sequentially column-by-column to the differential amplifier 246 (FIG. 2), which subtracts the reset and integrated charge signals and sends them to the analog-to-digital converter (ADC) 248 (FIG. 2). A plurality of ADC's 248 may also be provided, each digitizing sampled and held signals from one or more columns 249.
FIG. 4 illustrates a portion of the sample and hold circuit 261 of FIG. 3 in greater detail. The sample and hold circuit 261 holds a set of signals, e.g., a reset signal Vrst and an integrated charge signal Vsig from a desired pixel. For example, a reset signal Vrst of a desired pixel on column line 170 is stored on capacitor 228 and the integrated charge signal Vsig is stored on capacitor 226.
The operation of the circuits illustrated in FIGS. 1-4 is now described with reference to the simplified signal timing diagram of FIG. 5. During an image integration/acquisition period 290 the Row Sel signal on the row select line 160 is set to a logic low level to disable the row select transistor 188 and isolate the pixel 150 from the column line 170.
A readout period 298 for pixel 150 is separated into a readout period 292 for the readout of the reset signal, and a readout period 294 for the readout of the integrated charge signal. To begin the overall readout period 298, the row select signal on the row select line 160 is set to a logic high level to enable the row select transistor 188 and couple the pixel 150 to the column line 170. Just prior to readout, the reset control signal Reset is pulsed onto line 183, whereby the reset transistor 184 is activated and node A of the pixel 150 is reset by the reset voltage Vpix. To begin the reset signal readout period 292, the reset voltage Vpix on node A is transferred to the column line 170 via source follower transistor 186 and row select transistor 188 and stored in capacitor 228 when the SHR pulse is applied to switch 220 (FIG. 4) of the sample and hold circuit 261. Thus, the reset signal (Vrst) of the desired pixel 150 is sampled and stored on capacitor 228. After the reset signal Vrst is stored, the reset readout period 292 ends.
After the reset readout period 292 ends, an integrated charge signal readout period 294 begins. Transfer transistor 190 is enabled by a transfer control signal TX1 being pulsed on line 191. The integrated charge which has been integrating at photodiode 162 is transferred onto node A. Subsequently, the integrated charge signal on node A is transferred onto the column line 170 via source follower transistor 186 and row select transistor 188 and stored in capacitor 226 when an SHS signal is applied to switch 222 (FIG. 4) of the sample and hold circuit 261. That is, capacitor 226 stores the integrated charge signal Vsig. The integrated charge signal readout period 294 and the readout period 298 are completed. Just prior to the next integration/acquisition period 290, the row select signal on the row select line 160 is set to a logic low level to disable the row select transistor 188 and isolate the pixel 150 from the column line 170. Node A of pixel 150 is reset by reset voltage Vpix during the reset period 296. The transfer control signal TX1 can also be optionally pulsed during the reset period 296 to clear out any residual charge in the photodiode 162.
FIG. 6 depicts a portion of a shared floating diffusion pixel array 230′. The pixel array 230′ would typically have M×N shared pixels circuits 150′, where each shared pixel circuit 150′ has a shared floating diffusion node A, reset transistor 184, source follower transistor 186, and row select transistor 188. In addition, each shared pixel 150′ has transfer transistors 190, 190a, and photodiodes 162, 162a respectively coupled to the transfer transistors 190, 190a. Each photodiode, e.g., 162, and associated transfer transistor, e.g. 190, make up an imager pixel, which shares a pixel readout circuit with one or more other pixels. FIG. 6 illustrates a two way shared pixel circuit 150′, but other shared arrangements, e.g., 4-way shared and others, could also be used.
Pixel circuit 150′ is similar in architecture to pixel 150 of FIGS. 1 and 2, with a difference in that circuit 150′ has several photodiodes 162, 162a switchably coupled through respective transfer transistors 190, 190a to a common floating diffusion node A. Although FIG. 6 is shown with two rows of pixels, e.g., the pixel including photodiode 162 and the pixel including photodiode 162a, implementation of the array 230′ is, as noted, not limited to a two-way shared arrangement. Array 230′ includes the TX1a transfer control line, 191a to control the transfer transistor 190a. A readout operation of circuit 150′ is similar to the readout operation described above in FIGS. 1-5 with reference to circuit 150 except that node A is reset in between the readout from the photodiode 162 and the photodiode 162a. 
There exists an ever present need to reduce the size of imagers, yet, it is also desirable to more effectively use the die area within pixels without significantly increasing pixel circuitry. It is also desirable to improve pixel fill factor by using a larger area of the pixel for the photodiode.